1. Field of the Invention
The present invention relates to an operation timing verifying apparatus and program for verifying operation timings of a semiconductor integrated circuit in design.
2. Description of the Related Art
In the manufacture of semiconductor integrated circuits, elements such as transistors and connection lines are becoming increasingly fine. As elements become finer, the delay time of transistors decreases, but as to connection lines, line-to-line capacitances increase due to the shrinkage of line intervals, and in addition line resistances increase due to reduction in line cross-section area, and hence the delay time of connection lines tends to increase.
Meanwhile, in the design of a semiconductor integrated circuit, its operation timings need to be verified taking into account production variations of elements such as transistors and of lines. Factors in element variation include variations in processed sizes, in temperature, and in power supply voltage, and factors in line variation include variations in line widths, film thickness, in interlayer film thickness, in insulator permittivity, and in temperature.
In a conventional operation timing verifying method, operation timings of a circuit are verified in the respective conditions that the delay times of the entire circuit are minimal and maximal, each of the conditions being a combined condition of the line R/C net list derived condition that line capacitances and line resistances are minimal or maximal and the logic cell delay library derived condition that the delay times of logic cells such as arithmetic circuits are minimal or maximal. Here, the condition that the delay times of the entire circuit are minimal is referred to as the best corner, and the condition that the delay times of the entire circuit are maximal is referred to as the worst corner.
In Japanese Patent Application Kokai No. H10-240796 (Reference 1), there is disclosed a circuit simulation technique for variation analysis where variations in electrical characteristic values are reflected which are process data corresponding to line capacitances, line resistances, and the like. In Japanese Patent Kokai No. 2005-141434 (Reference 2), there is disclosed a timing verifying technique for highly accurate timing verification taking into account all combinations of various corner conditions and in which particular corner conditions corresponding to a design restriction for paths are selected from multiple actually possible corner conditions, thereby avoiding waste.